L440GX+ BIOS Release Notes NOTES: These notes apply to L440GX+ Production BIOS 9.1 and later: - L440GX+ Production BIOS 9.1 and later can be used on all L440GX+ server boards. However, BIOS support for the Pentium(r) III 600E MHz and faster processors can only be used on L440GX+ boards that have a PBA# of 704293-501 and greater or an AA# of 721242-008 and greater. Intel Pentium(r) III 600E MHz and faster processors are not supported on L440GX+ boards with PBA and AA numbers prvious to those listed. Intel Pentium(r) III processors upto and including 600 MHz(no 'E') can be used on all L440GX+ boards. - If an Intel Astor2 server chassis is used, the firmware of the Hot Swap Backplane must be upgraded to version 0.11 or later. BLD Date L440GX+ ---------------------------------------------------------------------- 125 06/06/00 L440GX+ Production Release 13.0 (Posted/Factory ECO) Based on BUILD 124 1. Banner roll for Production Release 13.0. ---------------------------------------------------------------------- 124 06/01/00 L440GX+ Beta 4.0 P13.0 (Release Candidate 2) Based on BUILD 122 1. Added microcode for C-0 Pentium III 0.18u Processors. 2. Due to problems with Build 123, this is based off of Build 122. ---------------------------------------------------------------------- 122 05/05/00 L440GX+ Beta 2.0 P13.0 (Release Candidate) Based on BUILD 121 1. Made a fix in BIOS for issue with Adaptec* ARO card where "Forced Decompression" was displayed. 2. Fixed issue with improperly programmed Board Version numbers. ---------------------------------------------------------------------- 121 04/21/00 L440GX+ Beta 1.0 P13.0 Based on BUILD 120 1. Support for 1GHz Pentium III Processors. NOTE: All .18u Pentium III B0 stepping QSpec parts are clock locked. 2. Fixed issue where 640K Base Memory test was being overwritten on POST Diagnostic screen. 3. Fixed issue with speed mismatched processors not being disabled. Now, the slower of the 2 processors will be disabled on reboot. This has a side effect of not allowing and unlocked processor that was set a different speed having a locked processor added to the configuration. 4. Fixed issue where CMOS was not being properly restored when corrupted. 5. Fixed issue where 133MHz FSB processors were being allowed to operate in the system. NOTE: This feature does not work with Q spec part but will work with S spec and production parts. 6. Added feature to prevent boards lower that FAB7 from booting processors faster than 850MHz. 7. Upgraded PXE 0.99c option ROM to PXE 2.x Build 78. ---------------------------------------------------------------------- 120 04/13/00 L440GX+ Production Release 12.3 (Post Only) Based on BUILD 119 1. Banner roll for Production Release 12.3. ---------------------------------------------------------------------- 119 04/12/00 L440GX+ BETA 1.0 P12.3 Based on BUILD 118 1. Additional fix for mixed steppings. ---------------------------------------------------------------------- 118 04/05/00 L440GX+ Production Release 12.2 (Post Only) Based on BUILD 117 1. Added updated Japanese Setup translations. 2. Fixed issue where secondary HSC information would intermittently change in Server Management screen in Setup. 3. Fixed issue with mixing 681 A2 and 683 B0 processors of the same speed displaying a processor speed mismatch error erronously. ---------------------------------------------------------------------- 117 03/24/00 L440GX+ Beta 1.0 P12.2 Based on BUILD 116 1. Removed corrupted Japanese strings from Setup. They will appear in English until updated translations are provided. 2. Added support to display secondary HSC info in Server Management screen in Setup. ---------------------------------------------------------------------- 116 03/23/00 L440GX+ Alpha 1.0 P12.2 Based on BUILD 115 1. Added TI bridge errata fix for products using the riser with the PCI2031 bridge. This adds a new setup option under Adv. Chipset to enable the fix. It is disabled by default. 2. Fixed WOR for COM2 under ACPI OS. 3. Fixed INT15h handler for microcode updates. Now multiple processors can be updated. 4. Fixed virus protection and Master Boot Record write protect feature. Now, these will only protect the hard drive when booted from a floppy. 5. Fix for PME handling. Some routines in the BIOS were not properly reading power management capabilities from the PIIX4E. ---------------------------------------------------------------------- 115 03/17/00 L440GX+ Production Release 12.1 (Posted / Factory ECO) Based on BUILD 114 1. Banner roll for Production Release 12.1. 2. Fix for Pentium(r) III processor support check. Previous algorithm only checked for baseboard PBA numbers, the new algorithm also checks for baseboard AA numbers. 3. Fix for Intel manufacturing test issue. Support for the 250MHz EEMUX setting has been added back. ---------------------------------------------------------------------- 114 03/14/00 This BIOS build was never released outside of Intel. ---------------------------------------------------------------------- 113 03/07/00 L440GX+ Beta 6.0 P12.0 (Release Candidate) Based on BUILD 112 1. Fix for 650MHz Pentium(r) III processors coming up at 400MHz. 2. Cleaned up some checks for 66 versus 100 FSB since 440GX only supports 100MHz. 3. Fixed DMI Mux programming routine to use new method incorporated in Build 110 rather than old method. ---------------------------------------------------------------------- 112 03/03/00 L440GX+ Beta 5.0 P12.0 Based on BUILD 110 1. POST was not displaying the correct processor speed when 850MHz processors were installed. The latest Phoenix CPU speed table of tolerances was pulled in so that the correct processor speed is displayed. ---------------------------------------------------------------------- 110 03/02/00 L440GX+ Beta 4.0 P12.0 Based on BUILD 108 1. 850MHz code was totally broken. Ported CPU speed settings from H820. Now, when a locked CPU is installed, the processor speed pick list will be hidden and only the POST processor speed will be shown. 2. Added back string that was deleted in Setup for Console redirection. ---------------------------------------------------------------------- 108 02/29/00 L440GX+ BETA 3.0 P12.0 Based on BUILD 107 1. Fixed issue with multiple, identical cards with option ROMs installed having issues with Multiboot. 2. Fixed issue with SEL logging of SBE and MBEs. The DIMM# will now be displayed in OEM Data 2 rather than FFh. ---------------------------------------------------------------------- 107 02/18/00 L440GX+ BETA 2.0 P12.0 Based on BUILD 106 1. Added warning msg that Console redir is disabled when Diags Screen is disabled to Setup. 2. Fixed identification of ECC versus non-ECC memory on POST screen. This was only a labelling issue and does not affect functionality. 3. Fixed 8188 reported. Works properly now. 4. Fixed DMI Type 0 BIOS ID. 5. Added support for 850MHz Coppermine. 6. Added new feature to prevent a Coppermine processor from booting on a Fab4 or lower board. 7. Fixed issue with Diags screen being in graphics mode for all languages other than English or Japanese. This would prevent console redirection from working. 8. HCT 9.5 ACPI Power button test. 9. Fix for POST hang after entering Setup from Multiboot menu and exiting without saving changes. 10. Removed FLOPPY from Multiboot menu. Now under "Removable Devices". 11. Fixed Pentium III branding 'E' to only show up on 550 and 600 processors per BIOS guide. 12. Removed various leftover debug outputs to Port 80h. These were undocumented. 13. Removed SMM_DEBUG component. This would cause an undocumented debug screen to appear under certain types of CMOS corruption. 14. Added fix to clear the PME# status bits when entering S0. This addresses an issue on the HCT 9.5 Pre-OS Foxfire test. 15. Fix for WHQL PCI 2.1 Cards test. Programming Subsystem Vendor and Device IDs for the integrated Adaptec SCSI controller. 16. Fix for when critical POST errors occur that halt the system. Previously, if the Quietboot logo was enabled, the system would halt with the Logo displayed and the system would appear to be hung and the error message could not be seen. Now, the logo will be clear and text restore prior to halt. ---------------------------------------------------------------------- 106 02/08/00 L440GX+ BETA 1.0 P12.0 Based on BUILD 105 1. Added microcode for 683 B-0 processor. ---------------------------------------------------------------------- 105 02/07/00 L440GX+ Production Release 11.2 (Posted/Factory ECO) Based on BUILD 104 1. Banner roll for Production 11.2 ---------------------------------------------------------------------- 104 02/03/00 L440GXx+ BETA 1.0 P11.2 Based on BUILD 102 1. Fix for PCI BusMastering being disabled for Slots 5/6. 2. Change copyright date on banner screen to 2000. 3. Fixed 0.18u Pentium III processorID from 'e' to 'E'. 4. Fix for extra 0 in memory display (i.e. - 2GB was being displayed as 20GB) ---------------------------------------------------------------------- 102 01/06/00 L440GX+ Production Release 11.1 (Posted/Factory ECO) Based on BUILD 101 1. Banner roll for Production 11.1 --------------------------------------------------------------------- 101 01/05/00 L440GX+Beta 1.0 P11.1 Based on BUILD 100 1. Fix for 440GX APG Jam Latch registers to enable more robust boards in slots 5 and 6 2. Language translation updates US not effected 3. Fix for Win 98 video memory in conflict different than WIN 2K ---------------------------------------------------------------------- 100 12/27/99 L440GX+ Production Release 11.0 (Post Only) Based on BUILD 99 1. Banner roll for Production 11.0 2. Minor fix for Int 15 DA20 for a function SSU no longer uses ---------------------------------------------------------------------- 99 12/14/99 L440GX+ Beta 4.0 P11 Based on BUILD 98 1. Fix for the Int 15 da20 9c call made by the SSU 2. String translations ---------------------------------------------------------------------- 98 12/07/99 L440GX+ Beta 3.0 P11 Based on BUILD 97 1. Add 800Mhz to setup and DMI strings ---------------------------------------------------------------------- 97 12/06/99 L440GX+ Beta 2.0 P11 Based on BUILD 96 1. Fix to 750Mhz DMI and setup strings 2. Fix to DMI type 4 problem in Bld 95 3. Fix to IBUAPI problem in bld 95 ---------------------------------------------------------------------- 96 11/30/99 L440GX+ Beta 1.0 P11 Based on BUILD 95 - Fixes - - Missing error description in BIOS when system configuration gets corrupted - Error in override for OEM error table - Japanese Language support fails at POST and re-entering BIOS setup - LS-120 Boot support not installed. - 3M Matsushita LS-120 fails to work properly as replacement for floppy drive - Cannot update microcode in an MP configuration - [PC 98] v. 8.1 Unreported Memory test fails - Screen blanks when moving from Language field another menu in BIOS setup - Need NMI source table entry of Multiple APIC description table[X] - Mutiboot on L440GX+ - 750 Mhz Coppermine support - Fixes found on NS for the VPD redundency - Fixes found on NS for the 8188 error code Microcode Updates Processor Update Revisions: Pentium(R) II processor: Patch ID 40 for A0-step, CPUID 650 Patch ID 40 for A1-step, CPUID 651 Patch ID 2A for B0-step, CPUID 652 Patch ID 10 for B1-step, CPUID 653 Pentium(R) III processor: Patch ID 10 for B0-step, CPUID 672 Patch ID 0e for C0-step, CPUID 673 Patch ID 14 for a0-step, CPUID 680 Patch ID 0d for a2-step, CPUID 681 ---------------------------------------------------------------------- 95 10/27/99 L440GX+ Beta 1.0 P10.1 1. Based on BUILD 94 2. Fix for 256Mb Technology DIMM support. Changed refresh rate to 7.8u ------------------------------------------------------------------------- 94 9/27/99 L440gx+ Production Release 10.0 (Post Only) 1. Based on BUILD 93 2. Banner roll to Production 10.0 ---------------------------------------------------------------------- 93 9/16/99 L440GX+ Beta 2.0 P10.0 1. Based on BUILD 90 2. Microcode update for 0.18u Pentium III A2 stepping 3. Added fix for unreported memory - I/O for WIN 2K* and Win98* HCT tests ---------------------------------------------------------------------------- 92 9/16/99 L440GX+ Production 9.2 (Posted/Factory ECO) 1. Based on BUILD 89 2. Microcode update for 0.18u Pentium III A2 stepping ---------------------------------------------------------------------- 90 9/06/99 L440GX+ Beta 1.0 P10.0 1. Fix for Enabling fixed disk boot sector write protect option fails 2. System hangs during POST when two DAC1100 RAID cards are instal This fix involves new PNP core code Moduls ---------------------------------------------------------------------- 89 8/31/99 L440GX+ Production Release 9.1 (Post Only) 1. Based on Build 87 2. Added Setup support 700Mhz 3. Banner roll and OEM rev roll for ACPI ---------------------------------------------------------------------- 87 8/30/99 L440GX+ Beta 1.0 P9.1 1. Based on Build 86 2. Moved the location of the BUD since it is in conflict with the ISC utilities ---------------------------------------------------------------------- 86 8/20/99 L440GX+ Production Release 9.0 (Never released) 1. Fix for POST processor strings 2. Fix for max CPU speed of 650. ---------------------------------------------------------------------- 85 8/19/99 L440GX+ Beta 2.0 P9.0 1. Updated Video BIOS for 2MB SGRAM 2. Updated DMI table for 650. ---------------------------------------------------------------------- 84 8/18/99 L440GX+ Beta 1.0 P9.0 1. Based on Build 82 2. Added 0.18u Pentium III (Coppermine) support ---------------------------------------------------------------------- 82 8/17/99 L440GX+ Production Release 8.0 (Never released) **NOTE: Astor2 server chassis will require the latest HSC 0.11 FW for this release 1. Based on Build 80 2. Banner roll for Production Release 8.0 ---------------------------------------------------------------------- 80 8/13/99 L440GX+ RC3 Beta 8.0 **NOTE: Astor2 server chassis will require the latest HSC 0.11 FW for this release 1. Based on Build 78 2. Fix for Win 2K install with varios Raid cards Uses PIC mode with PRT for the ASL code ----------------------------------------------------------------------- 78 8/09/99 L440GX+ RC2 Beta P8.0 **NOTE: Astor2 server chassis will require the latest HSC 0.11 FW for this release 1. Based on Build 77 2. Fix for SCSI BIOS BBS issue Now V2.20S1B1 V2.20S1 would not ID the SCSI Hard drives ----------------------------------------------------------------------- 77 7/28/99 L440GX+ RC1 Beta P8.0 **NOTE: Requires HSC FW 0.10 for this release when astor2 SCSI backplane is used 1. Based on Build 75 2. 17435 - changed back to having "Disable" for COM1, COM2 3. 18074 - Fix for unreported memory test failure with HDG test 4. 17803 - SMBIOS structure fixes SLOT 1 Processor Update Revisions: Pentium(R) II processor: Patch ID 40 for A0-step, CPUID 650 Patch ID 40 for A1-step, CPUID 651 Patch ID 2A for B0-step, CPUID 652 Patch ID 10 for B1-step, CPUID 653 Pentium(R) III processor: Patch ID 0c for B0-step, CPUID 672 Patch ID 0a for C0-step, CPUID 673 ---------------------------------------------------------------------- 75 7/22/99 LW Beta release candidate P8.0 **NOTE: Astor2 requires HSC 0.11 FW for this release 1 Based on Build 73 2 Added latest Microcode Patches for 672 and 673 3 Remove the disable of COM1 and COM2 from setup menu 4 Remove Base memory test from setup 5 Changed Logo screen for "server board" instead of mother board 6 Changed escape method for logo screen and extended memory test 7 added Intel(R) to post screen ---------------------------------------------------------------------- 73 7/12/99 Beta release candidate P8.0 **NOTE: Need latest HSP FW for this release when a SCSI backplane is used Description: 1 Fix for PC 28 Hang problem turn Memory clocks off for SPD reads in BIOS Release 7.3 2 Added fix for FW update mode causing NMI 3 Added Fast Memory test interface 4 Int 15 test with wrong reg 5 Fix strings for SMBIOS 6 Fix Post strings 7 WIN 2K HDG requirements 8 B0 and C0 Deschuts P6 updates 9 New SCSI BIOS 2.20 10 Remove PERR enable/disable from Setup --------------------------------------------------------------------- 72 7/01/99 Production Release 7.3 (Post Only) 1. Based on BUILD 71 2. Banner roll to 7.3 71 7/01/99 Beta RC 7.3 1. Based on BUILD 69 2. Added workaround for problem found with warm boots hanging at PC 28h 69 6/23/99 Production Release 7.2 (Post Only) 1. Based on BUILD 68 2. Banner roll for Production 68 6/23/99 Beta RC 7.2 1. Based on BUILD 67 2. Updated SMM code to correctly handle SBE, and SERR 67 6/11/99 Beta RC 7.1 1. Based on BUILD 66 2. Added Pentium III 600Mhz support to setup 3. Added fix for FW update mode causing NMI NOTE: L440GX+ BIOS RC7.1 was created for test purposes only. It will not be made into a production release nor will it be inplemented into our factories. The sole purpose of this BIOS is to allow testing of the Q-spec pre-production Pentium(R) III 600MHz processor. 66 6/04/99 Production Release 7.0 (Posted / Factory ECO) 1. Based on BUILD 62 2. Banner roll for P7.0 build 66 62 5/14/99 Beta 2.0 release for Candidate P7.0 1. Based on BUILD 60 2. added WIN 2K 2Gig fix. 16417 3. Added additional feature for loging errors on Flash Parameter block corruption 61 5/12/99 Release 6.1 1. Based on BUILD 58 does not include DMI fix 2. added WIN 2K 2Gig fix. 16417 60 5/11/99 Beta 1.0 release for Candidate P7.0 1. NEC DMI Vital Data Protection 17104 2. New Adaptec BIOS for MO not booting problem 15667 3. PEP minor string fix up 16478 4. Bug fix for L2 Cache Reg not set correctly problem found on NS 58 4/20/99 Release P6.0 roll banner for production 6.0 57 4/20/99 Beta release for Candidate P6.0 Added new Microcode Patch for C0 673 55 4/12/99 Beta release for Candidate P6.0 1. Added fix for clocking 550Mhz processor 16713 2. Added fix for logging SERR in SEL 16662 3. Added fix for Type 1,2,3 more robust and 16398 type 6 and type 17 for > 512 Memory fix 16198 4. Added string fix for PEP Black out period 16518 5. Added fixes for the C0 stepping cache initialization 53 3/11/99 Production Release L440GX+ P5.0 51 3/02/99 N/A LW ECO Slot 1 related changes 50 3/01/99 Bad Build 47 2/16/99 Production Release 4.0 46 2/12/99 RC 5 - Trans for Japanese PSN 44 2/11/99 RC 4 -Translations for PSN Fix 43 2/11/99 RC 3 - Reverse the order of the slot for the error logging on DIMM 41 2/09/99 RC 2 -Added PIIX4 precharging code to avoid long IDE drive detection 40 2/09/99 RC 1- 1 Added processor serial number PSN en/disable option to Setup. 2 DMI type 6 and type 17 handler bug Correctly interpret size word returned by chipset 38 2/02/99 Roll Banner for Production Release 3.0 36 1/27/99 LW ECO 1. Fix for Slot 1 and Slot 2 CPU updates 2. Added PEP and Mt Bachelor Features for Eval 35 1/20/99 Production Release 2.0 1. Fix for NT4.0 Greater than 1 gig memory (wrong Microcode) 2. Pentium III string change and copyright 1999 34 1/19/99 LW ECO 2. Fix for S1 with LW from previous 3. Fix for CPU speed on setup menu. 4. No PEP or Mt Bachelor features 31 1/14/99 LW ECO Beta P1.0 1. change copyright year 1999 4. Set devices behind bridge 7. No PEP or Mt Bachelor features 30 1/05/99 LW ECO PEP Based on Production 1.0 LW Added PEP features 29 12/18/99 Production Release 1.0 LW