Intel Xscale DBPXA27XC0

Overview

RedBoot supports the FFUART on the CPU card and the built-in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 32MB boot flash on the CPU card.

The following RedBoot configurations are supported:

Initial Installation Method

The board manufacturer provides a Windows application which is capable of programming the flash over JATG interface using the PC parallel port. This application is necessary for initial installations of RedBoot. Please see the board manual for more information on using this utility. In general, the process involves programming the ROM mode RedBoot image to flash address 0x00000000.

After booting the initial installation of RedBoot, this warning may be printed:
flash configuration checksum error or invalid key
This is normal, and indicates that the flash must be configured for use by RedBoot. Even if the above message is not printed, it may be a good idea to reinitialize the flash anyway. Do this with the fis command:
RedBoot> fis init
About to initialize [format] FLASH image system - continue (y/n)? y
*** Initialize FLASH Image System
    Warning: device contents not erased, some blocks may not be usable
... Unlock from 0xf1fc0000-0xf2000000: .
... Erase from 0xf1fc0000-0xf2000000: .
... Program from 0x03fbf000-0x03fff000 at 0xf1fc0000: .
... Lock from 0xf1fc0000-0xf2000000: .
followed by the fconfig command:
RedBoot> fconfig -i
Initialize non-volatile configuration - continue (y/n)? y
Run script at boot: false
Use BOOTP for network configuration: true
Console baud rate: 115200
DNS server IP address: 
GDB connection port: 9000
Force console for special debug messages: false
Network debug at boot time: false
Update RedBoot non-volatile configuration - continue (y/n)? y
... Unlock from 0xf1f80000-0xf1f81000: .
... Erase from 0xf1f80000-0xf1f81000: .
... Program from 0x03fb2000-0x03fb3000 at 0xf1f80000: .
... Lock from 0xf1f80000-0xf1f81000: .

Switch Settings

The DBPXA27XC0 board is configurable through a number of switches and jumpers. RedBoot makes some assumptions about board configuration and attention must be paid to these assumptions for reliable RedBoot operation.


   Baseboard: SW1, SW2 - dot
   CPU board: SW3 - dot

CPU core speed is set through the rotary hex switch SW9 on the DBPXA27XC0 board:

   Value   Core (MHz)
   -----   ----------
     0        91.0
     1        39.0
     2        65.0
     3        91.0
     4       117.0
     5       143.0
     6       169.0
     7       195.0

LED Codes

RedBoot uses the 8 digit LED display to indicate status during board initialization. Possible codes are:

LED     Actions
-------------------------------------------------------------
   Power-On/Reset
        Set the CPSR
        Enable coprocessor access
        Drain write and fill buffer
        Setup GPIO lines
        Setup PBIU chip selects
25000FFF
        Delay 200usec
24000FFF
        Initialize MSCx registers
        Initialize MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1
24100FFF
        Initialize MDREFR
24200FFF
        Initialize SXCNFG
24300FFF
        Initialize MDCNFG
24400FFF
        Trigger SDRAM refresh cycles
24500FFF
        Enable SDRAM partitions
24600FFF
        Enable SDRAM auto-powerdown
25800FFF
        Setup clocks
25820FFF
        Frequency change
25830FFF
        Setup page table
25830FFF
        Setup domain permissions
25840FFF
        Turn on MMU
25850FFF
        Enable D-Cache
00000000
        Start up the eCos kernel or RedBoot

Rebuilding RedBoot

These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:
export TARGET=dbpxa27xc0
export ARCH_DIR=arm
export PLATFORM_DIR=xscale/dbpxa27xc0

The names of configuration files are listed above with the description of the associated modes.

Interrupts

RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype::
int irq_handler( unsigned vector, unsigned data )
On the DBPXA27XC0 board, the vector argument is one of many interrupts defined in hal/arm/xscale/pxa270/current/include/hal_var_ints.h::
#define CYGNUM_HAL_INTERRUPT_SSP3          0
#define CYGNUM_HAL_INTERRUPT_MSL           1
#define CYGNUM_HAL_INTERRUPT_USB_HOST2     2
#define CYGNUM_HAL_INTERRUPT_USB_HOST1     3
#define CYGNUM_HAL_INTERRUPT_KEYPAD        4
#define CYGNUM_HAL_INTERRUPT_MEMSTICK      5
#define CYGNUM_HAL_INTERRUPT_POWER_I2C     6
#define CYGNUM_HAL_INTERRUPT_TIMERX        7
#define CYGNUM_HAL_INTERRUPT_GPIO0         8
#define CYGNUM_HAL_INTERRUPT_GPIO1         9
#define CYGNUM_HAL_INTERRUPT_GPIO2_120     10
#define CYGNUM_HAL_INTERRUPT_USB_CLIENT    11
#define CYGNUM_HAL_INTERRUPT_CORE_PMU      12
#define CYGNUM_HAL_INTERRUPT_I2S           13
#define CYGNUM_HAL_INTERRUPT_AC97          14
#define CYGNUM_HAL_INTERRUPT_USIM          15
#define CYGNUM_HAL_INTERRUPT_SSP2          16
#define CYGNUM_HAL_INTERRUPT_LCD           17
#define CYGNUM_HAL_INTERRUPT_I2C           18
#define CYGNUM_HAL_INTERRUPT_ICP           19
#define CYGNUM_HAL_INTERRUPT_STUART        20
#define CYGNUM_HAL_INTERRUPT_BTUART        21
#define CYGNUM_HAL_INTERRUPT_FFUART        22
#define CYGNUM_HAL_INTERRUPT_FLASH         23
#define CYGNUM_HAL_INTERRUPT_SSP1          24
#define CYGNUM_HAL_INTERRUPT_DMA           25
#define CYGNUM_HAL_INTERRUPT_TIMER0        26
#define CYGNUM_HAL_INTERRUPT_TIMER1        27
#define CYGNUM_HAL_INTERRUPT_TIMER2        28
#define CYGNUM_HAL_INTERRUPT_TIMER3        29
#define CYGNUM_HAL_INTERRUPT_HZ            30
#define CYGNUM_HAL_INTERRUPT_ALARM         31
#define NOT_USED_32                        32
#define NOT_USED_33                        33
#define CYGNUM_HAL_INTERRUPT_GPIO2         34
...
#define CYGNUM_HAL_INTERRUPT_GPIO120       152
#define CYGNUM_HAL_INTERRUPT_MMC_CARD      153
#define CYGNUM_HAL_INTERRUPT_USIM_CARD     154
#define CYGNUM_HAL_INTERRUPT_USB_CABLE     155
#define CYGNUM_HAL_INTERRUPT_ETHERNET      156
#define CYGNUM_HAL_INTERRUPT_AC97_CODEC    157
#define CYGNUM_HAL_INTERRUPT_PEN           158
#define CYGNUM_HAL_INTERRUPT_MS_INSERT     159
#define CYGNUM_HAL_INTERRUPT_EXBRD         160
#define CYGNUM_HAL_INTERRUPT_RSVD8         161
#define CYGNUM_HAL_INTERRUPT_PCMCIA0_CARD  162
#define CYGNUM_HAL_INTERRUPT_PCMCIA0_STAT  163
#define CYGNUM_HAL_INTERRUPT_PCMCIA0       164
#define CYGNUM_HAL_INTERRUPT_RSVD12        165
#define CYGNUM_HAL_INTERRUPT_PCMCIA1_CARD  166
#define CYGNUM_HAL_INTERRUPT_PCMCIA1_STAT  167
#define CYGNUM_HAL_INTERRUPT_PCMCIA1       168
The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 169 interrupts, the data table starts at address 0x82a8.

An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot.

Memory Maps

The RAM based page table is located at RAM start + 0x4000.

X C B  Description
- - -  ---------------------------------------------
0 0 0  Uncached/Unbuffered
0 0 1  Uncached/Buffered
0 1 0  Cached/Buffered    Write Through, Read Allocate
0 1 1  Cached/Buffered    Write Back, Read Allocate
1 0 0  Invalid -- not used
1 0 1  Uncached/Buffered  No write buffer coalescing
1 1 0  Mini DCache - Policy set by Aux Ctl Register
1 1 1  Cached/Buffered    Write Back, Read/Write Allocate

Physical Address Range     Description
-----------------------    ----------------------------------
0x00000000 - 0x03ffffff    Boot flash          (nCS0)
0x04000000 - 0x07ffffff    Application flash   (nCS1)
0x08000000 - 0x080fffff    Baseboard registers (nCS2)
0x0a000000 - 0x0a1fffff    SRAM                (nCS2)
0x10000000 - 0x100fffff    Ethernet            (nCS4)
0x20000000 - 0x2fffffff    PCMCIA/CF Slot 0
0x30000000 - 0x3fffffff    PCMCIA/CF Slot 1
0x40000000 - 0x43ffffff    CPU memory-mapped registers
0x44000000 - 0x47ffffff    LCD memory-mapped registers
0x48000000 - 0x4bffffff    Memory controller registers
0x4c000000 - 0x4fffffff    USB host
0xa0000000 - 0xa3ffffff    SDRAM bank 0       (nSDCS0)
0xa4000000 - 0xa7ffffff    SDRAM bank 1       (nSDCS0)

 Virtual Address Map     X C B  Description
-----------------------  - - -  ----------------------------------
0x00000000 - 0x07ffffff  1 1 1  SDRAM
0x08000000 - 0x080fffff  0 0 0  Baseboard registers (nCS2)
0x0a000000 - 0x0a1fffff  1 1 1  SRAM                (nCS2)
0x10000000 - 0x100fffff  0 0 0  Ethernet            (nCS4)
0x20000000 - 0x2fffffff  0 0 0  PCMCIA/CF Slot 0
0x30000000 - 0x3fffffff  0 0 0  PCMCIA/CF Slot 1
0x40000000 - 0x43ffffff  0 0 0  CPU memory-mapped registers
0x44000000 - 0x47ffffff  0 0 0  LCD memory-mapped registers
0x48000000 - 0x4bffffff  0 0 0  Memory controller registers
0x4c000000 - 0x4fffffff  0 0 0  USB host
0xa0000000 - 0xa7ffffff  0 0 0  Uncached SDRAM alias
0xa8000000 - 0xa80fffff  1 1 1  D-cache flush region (no phys mem)
0xf0000000 - 0xf3ffffff  0 1 0  Boot flash          (nCS0)
0xf4000000 - 0xf7ffffff  0 1 0  Application flash   (nCS1)

Platform Resource Usage

The PXA270 programmable OStimer0 is used for timeout support for networking and XModem file transfers.