RedBoot™ User's Guide: Document Version 1.9, February 2003 | ||
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RedBoot supports the board serial ports attached to UART1 and UART3. Both channels are used for the RedBoot prompt et al, and you can connect using GDB to either.
The default serial port settings are 38400,8,N,1.
RedBoot supports FLASH management on the Plc2. Three basic RedBoot configurations are supported: RedBoot running from the board's FLASH boot sector ("ROM"), RedBoot running at address 0x40000 in the FLASH ("POST") - for cooperation with customer POST code - and normal eCos RAM startup.
A Linux utility "Jflash" is used to program FLASH over a parallel port driven JTAG interface. A special hardware box from ACN is required. After that, RedBoot can be managed and upgraded in the usual manner using its own flash management commands in the usual manner; "fis init" will fill in appropriate defaults for the flash addresses concerned.
The first level page table is located at physical address 0xc0004000. No second level tables are used.
NOTE: The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B).
Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x007fffff 8Mb flash (nCS0) 0x18000000 - 0x180fffff Altera FPGA and X-Bus (nCS3) 0x20000000 - 0x2fffffff PCMCIA slot 0 - LAN91C96 Ethernet 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc7ffffff DRAM Bank 0 0xc8000000 - 0xcfffffff DRAM Bank 1 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb 0x18000000 - 0x180fffff N N Altera FPGA and X-Bus (nCS3) 0x20000000 - 0x2fffffff N N PCMCIA slot 0 - LAN91C96 Ethernet 0x50000000 - 0x507fffff Y Y 8Mb flash (nCS0) 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc0ffffff N Y DRAM Bank 0:8 or 16Mb 0xc8000000 - 0xc8ffffff N Y DRAM Bank 1:8 or 16Mb or absent 0xe0000000 - 0xe7ffffff Y Y Cache Clean |
SDRAM can be any of
1 x 8Mb = 8Mb 2 x 8Mb = 16Mb
1 x 16Mb = 16Mb 2 x 16Mb = 32Mb
All are programmed the same way in the memory controller. Startup code detects which is fitted and programs the memory map accordingly. If the device(s) is 8Mb, then there are gaps in the physical memory map, because a high order address bit is not connected. The gaps are the higher 2Mb out of every 4Mb.
The SA11x0 OS timer is used as a polled timer to provide timeout support within RedBoot.
The instructions in Chapter 3 should be followed. The values for TARGET, ARCH_DIR and PLATFORM_DIR on this platform are “plc2”, “arm” and “sa11x0/plc2” respectively. Note that the configuration export files supplied in the hal/arm/sa11x0/plc2/VERSION/misc directory in the RedBoot source tree should be used.